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M37151M6 Datasheet(PDF) 32 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 32 of 136 REJ03B0129-0100Z 8.6.3 I2C Clock Control Register The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA automatically goes to LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA automatically goes to HIGH (ACK is not returned). ✽ACK clock: Clock for acknowledgement Fig. 8.6.4 I2C Clock Control Register (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00FA16] I2C Clock Control Register 0 to 4 SCL frequency control bits (CCR0 to CCR4) 7 5 6 SCL mode specification bit (FAST MODE) 0: Standard clock mode 1: High-speed clock mode 0 Standard clock mode Functions Name After reset RW B 0 0 0 ACK bit (ACK BIT) ACK clock bit (ACK) 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock High speed clock mode Setup disabled Setup disabled 00 to 02 Setup disabled 333 03 Setup disabled 250 04 100 400 (See note) 05 83.3 166 06 500/CCR value 1000/CCR value 17.2 34.5 1D 16.6 33.3 1E 16.1 32.3 1F ( φ = 4 MHz, unit : kHz) Note. At 400kHz in the high-speed clock mode, the duty is as below. “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4– CCR0 RW RW RW RW |
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