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M37151M6 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 30 of 136 REJ03B0129-0100Z 8.6.1 I2C Data Shift Register The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register 1(S0) [Address 00F616] After reset Functions Name B W R W R I2C Data Shift Register 0 to 7 This is an 8-bit shift register to store receive data and write transmit data. Indeterminate Note : To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. D0 to D7 |
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