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M37151M6 Datasheet(PDF) 26 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 26 of 136 REJ03B0129-0100Z 8 Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate: Connect to black side at reset. Synchronous circuit Frequency divider 1/8 1/4 1/16 SM1 SM0 Serial I/O counter (8) SM5 : LSB MSB S SM2 1/2 XIN SIN SOUT SCLK 1/2 XCIN 1/2 CM7 1/2 Note : When the data is set in the serial I/O register (address 00EA (See note) CM : CPU mode register SM : Serial I/O mode register 16 ), the register functions as the serial I/O shift register. P20 Latch SM3 P21 Latch SM3 SM6 8.5 SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchro- nous clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P20–P22. Bit 3 of the serial I/O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to “0.” Fig. 8.5.1 Serial I/O Block Diagram The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. |
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