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M37151M6 Datasheet(PDF) 18 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 18 of 136 REJ03B0129-0100Z (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe- riod. Set bit 0 of the PWM mode register 1 to “0.” (6) Data slicer interrupt An interrupt occurs when slicing data is completed. (7) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (8) Timer 5 • 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (9) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request |
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