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M37151M6 Datasheet(PDF) 15 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 15 Page - Renesas Technology Corp |
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15 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 15 of 136 REJ03B0129-0100Z Fig. 8.2.4 Memory Map of Special Function Register 2 (SFR2) sSFR2 Area (addresses 20016 to 20F16) b7 b0 b7 b0 20016 20116 20216 20316 20416 20616 20516 20716 20816 20916 20B16 20C16 20D16 20E16 20A16 20F16 210 211 212 PWM2 register (PWM2) PWM4 register (PWM4) PWM0 register (PWM0) PWM1 register (PWM1) PWM3 register (PWM3) Clock frequency set register (CFS) PWM mode register 2 (PM2) ROM correction address 1 (low-order) ROM correction enable register (RCR) PWM mode register 1 (PM1) ROM correction address 2 (high-order) ROM correction address 1 (high-order) ROM correction address 2 (low-order) Clock control register 2(CC2) Clock control register 3(CC3) : “0” immediately after reset : Indeterminate immediately after reset 0 1 ? <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) : <Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : 1 0 Address Register Bit allocation State immediately after reset 0 0 0 0016 0016 0016 0016 0016 0 0 0 0 1 1 1 0 ? ? ? ? 0 ? ? 0 0016 ? PM13 PM10 RC0 CC35 0016 PM23 PM20 PM24 PM21 PM22 RC1 0 1 0 0 0 1 0 0 CC37 0016 0016 0016 ? ? ? ? ? ? ? 0 0 0 0 0 0 ? |
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