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M37151M6 Datasheet(PDF) 69 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 69 Page - Renesas Technology Corp |
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69 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 69 of 136 REJ03B0129-0100Z Fig. 8.11.10 Block Diagram of Dot Size Control Circuit Fig. 8.11.11 Definition of Dot Sizes 1 do t Scanning line of F1(F2 ) Scanning line of F2(F1 ) 1/2 H 1 H 2 H 3 H 3T C 2T C 1T C 1T C Data slicer clock HSYNC f (OSC) OC3 or OC4 Synchronous circuit Pre-divide circuit Clock cycle = 1TC Cycle ✕ 2 “0” Cycle ✕ 3 “1” BCi4 Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1. Horizontal dot size control circuit Vertical dot size control circuit OSD control circuit ” “0” “1” OC7 8.11.2 Dot Size The dot size can be selected in block units. The vertical dot size is determined by dividing HSYNC in the vertical dot size control circuit. The horizontal dot size is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, f (OSC) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of each block is specified by bits 2 to 4 of block control register i. Refer to Figure 8.11.4 for the structure of the block control register. The block diagram of the dot size control circuit is shown in Figure 8.11.10. The pre-divide ratio is specified by bit 7 of the OSD control register (address 00D016) and bit 4 of block control register i (addresses 00D216 and 00D316) . When bit 7 of the OSD control register (address 00D016) is set to "0," the double or triple pre-divide ratio can be chosen per block unit by bit 4 of block control register i. And then, when it is set to "1", the pre-divide ratio increases 1 time (both blocks 1 and 2). The pre-di- vided dot size can be specified per block unit by bits 2 and 3 of block control register i. |
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