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M37151M6 Datasheet(PDF) 63 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 63 Page - Renesas Technology Corp |
63 / 138 page M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 63 of 136 REJ03B0129-0100Z Fig. 8.11.3 OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (OC) [Address 00D016] B Name Functions After reset R W OSD Control Register 0 OSD control bit (OC0) (See note 1) 0 : All-blocks display off 1 : All-blocks display on 0 1 Automatic solid space control bit (OC1) 0 : OFF 1 : ON 0 2 0 : OFF 1 : ON 0 0 4 OSD mode clock selection bit (OC4) 0 Window control bit (OC2) RW RW RW RW RW 3 0 : Data slicer clock 1 : Internal oscillating clock f(osc) CC mode clock selection bit (OC3) 0 : Data slicer clock 1 : Internal oscillating clock f(osc) 7 Pre-divide ratio selection bit (OC7) 0R W 0 : Divide ratio by the block control register 1 : Pre-divide ratios = ✕ 1 for blocks 1 and 2 5, 6 Fix these bits to “0.” 0 R W 0 0 Notes 1: Even this bit is switched during display, the display screen 2: This bit's priority is higher than BCi4 of Block Control Register i setting. remains unchanged until a rising (falling) of the next VSYNC (See note 2) |
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