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M37151M6 Datasheet(PDF) 59 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 59 Page - Renesas Technology Corp |
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59 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 59 of 136 REJ03B0129-0100Z Fig. 8.10.12 Sync Pulse Counter Register 8.10.13 Synchronous Signal Counter The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “1F16,” “1F16” is stored into the latch. Fig. 8.10.13 Synchronous Signal Counter Block Diagram The latch value can be obtained by reading out the sync pulse counter register (address 00E916). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 020816) is set to “0.” Figure 8.10.12 shows the structure of the sync pulse counter and Figure 8.10.13 shows the synchronous signal counter block diagram. b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E9 16] R W Sync Pulse Counter Register 0 to 4 0R 0R — — 6, 7 Count value (HC0 to HC4) 5 0R W Count source (HC5) 0: HSYNC signal 1: Composite sync signal B After reset Functions Name Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Reset 5-bit counter Latch (5 bits) f(XIN)/213 Composite sync signal HSYNC signal Counter Sync pulse counter register Data bus Selection gate : connected to black side when reset. b5 |
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