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M37151M6 Datasheet(PDF) 57 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 57 of 136 REJ03B0129-0100Z 8.10.10 Data Clock Generating Circuit This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores cap- tion data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling edge of the vertical synchronous signal (Vsep). Fig. 8.10.11 Data Clock Position Register b7 b6 b5 b4 b3 b2 b1 b0 Data clock position register (DPS) [Address 00E516] Data Clock Position Register 01 R W Fix this bit to “0.” 1 Fix this bit to “1.” 0 R W 10 0 B After reset Functions Name R W 3 Data clock position set bits (DPS3 to DPS7) 1 R W 4 to 7 0 2 Fix this bit to “0.” 0 R W |
Similar Part No. - M37151M6 |
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