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M37151M6 Datasheet(PDF) 51 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 51 Page - Renesas Technology Corp |
51 / 138 page ![]() M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 51 of 136 REJ03B0129-0100Z Figures 8.10.4 and 8.10.5 the data slicer control registers. Fig. 8.10.4 Data Slicer Control Register 1 Fig. 8.10.5 Data Slicer Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Data slicer control register 1(DSC1) [Address 00E016] Data Slicer Control Register 1 0 0 R W 0 R W 2 Reference clock source selection bit (DSC12) 0: Video signal 1: HSYNC signal 0 R W 0 R W 0R W 1 1 0: Stopped 1: Operating Data slicer and timing signal generating circuit control bit (DSC10) Fix these bits to “0.” 3, 4 0 0 0 1 0: F2 1: F1 Selection bit of data slice reference voltage generating field (DSC11) Fix these bits to “1.” 5, 6 Definition of fields 1 (F1) and 2 (F2) Hsep Vsep F1: Hsep Vsep F2: B After reset R W Name Functions 0 R W Fix this bit to “0.” 7 b7 b6 b5 b4 b3 b2 b1 b0 Data slicer control register 2 (DSC2) [Address 00E116] RW Data Slicer Control Register 2 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate R— 1 0 R W R — R — 01 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Caption data latch completion flag 1 (DSC20) Fix this bit to “1.” 2 Read-only Test bit 0 0: F2 1: F1 Field determination flag(DSC23) 0: Method (1) 1: Method (2) Vertical synchronous signal (Vsep) generating method selection bit (DSC24) 0 RW 5 0: Match 1: Mismatch V-pulse shape determination flag (DSC25) R— 6 4 0 R W Fix this bit to “0.” B 1 After reset Functions Name Definition of fields 1 (F1) and 2 (F2) Hsep Vsep F1: Hsep Vsep F2: R — 7 Read-only Test bit |
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