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M37151M6 Datasheet(PDF) 50 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 50 Page - Renesas Technology Corp |
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50 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 50 of 136 REJ03B0129-0100Z HLF VHOLD CVIN Open Open Leave HLF pin open. Leave V HOLD pin open. Pull-down CV IN pin to V SS through a resistor of 5 k Ω or more. 5 k Ω or more 24 25 26 Connect the same external circuit as when using data slicer to HLF pin. Leave V HOLD pin open. Pull-up CVIN to VCC through a resistor of 5 k Ω or more. VHOLD CVIN Open 5 k Ω or more HLF 1 k Ω 200pF 1 µF 24 25 26 8.10.1 Notes When not Using Data Slicer When bit 0 of data slicer control register 1 (address 00E016) is “0,” terminate the pins as shown in Figure 8.10.2. Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit are in OFF State When both bits 0 and 2 of data slicer control register 1 (address 00E016) are “1,” terminate the pins as shown in Figure 8.10.3. Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State <When data slicer circuit and timing signal generating circuit are in OFF state> <When using a reference clock generated in timing signal generating circuit as OSD clock> |
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