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M37151M6 Datasheet(PDF) 41 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 41 Page - Renesas Technology Corp |
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41 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 41 of 136 REJ03B0129-0100Z (3) RESTART condition generation procedure ➀ Procedure example (The necessary conditions for the procedure are described in ➁ to ➅ below.) Execute the following procedure when the PIN bit is “0.” • • LDM #$00, S1 (Select slave receive mode) LDA — (Take out slave address value) SEI (Interrupt disabled) STA S0 (Write slave address value) LDM #$F0, S1 (Trigger RESTART condition generation) CLI (Interrupt enabled) • • ➁ Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ➂ The SCL pin is released by writing the slave address value to the I2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. ➃ Use “LDM” instruction for setting trigger of RESTART condition generation. ➄ Write the slave address value of ➂ and set trigger of RESTART condition generation of ➃ continuously, as shown in the procedure example. ➅ Disable interrupts during the following two process steps: • Write slave address value • Trigger RESTART condition generation (4) STOP condition generating procedure ➀ Procedure example (The necessary conditions for the procedure are described in ➁ to ➃ below.) • • SEI (Interrupt disabled) LDM #$C0, S1 (Select master transmit mode) NOP (Set NOP) LDM #$D0, S1 (Trigger STOP condition generation) CLI (Interrupt enabled) • • ➁ Write “0” to the PIN bit when master transmit mode is selected. ➂ Execute “NOP” instruction after master transmit mode is set. Also, set trigger of STOP condition generation within 10 cycles after se- lecting the master trasmit mode. ➃ Disable interrupts during the following two process steps: • Select master transmit mode • Trigger STOP condition generation (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously as it may cause the SCL pin the SDA pin to be released after about one machine cycle. Also, do not execute an instruction to set the MST and TRX bits to “0” from “1” when the PIN bit is “1,” as it may cause the same problem. (6) Process after STOP condition generation Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. Doing so may cause the STOP condition waveform from being generated normally. Reading the registers does not cause the same problem. |
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