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M37151M6 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 39 of 136 REJ03B0129-0100Z 8.6.10 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz with the ACK return mode enabled, is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00FA16). ➂ Set “1016” in the I2C status register (address 00F816) and hold the SCL at HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00F916). ➄ Set the address data of the destination of transmission in the high- order 7 bits of the I2C data shift register (address 00F616) and set “0” in the least significant bit. ➅ Set “F016” in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ➆ Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆. ➈ Set “D016” in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. 8.6.11 Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, with the ACK Non-return mode enabled while using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit. ➁ Set the ACK non-return mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00FA16). ➂ Set “1016” in the I2C status register (address 00F816) and hold the SCL at HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00F916). ➄ When a START condition is received, an address comparison is executed. ➅ •When all transmitted address are“0” (general call): AD0 of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs. •When the transmitted addresses match the address set in ➀: ASS of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs. •In the cases other than the above: AD0 and AAS of the I2C status register (address 00F816) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2C data shift register (address 00F616). ➇ When receiving control data of more than 1 byte, repeat step ➆. ➈ When a STOP condition is detected, the communication ends. |
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