 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M37151M6 Datasheet(PDF) 36 Page - Renesas Technology Corp |
|
||||||||||||||||||||||||||||||
M37151M6 Datasheet(HTML) 36 Page - Renesas Technology Corp |
|
|
36 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 36 of 136 REJ03B0129-0100Z (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification in data communica- tions. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in any of the following conditions. • Immediately after completion of 1-byte data transmission when arbitration lost is detected • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication prevention function (Note). • At reset Fig. 8.6.8 I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00F816] I 2C Status Register 0 3 4 5 6, 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode 1 2 0 0 0 1 0 BName Functions After reset Communication mode specification bits (TRX, MST) 0 : Bus free 1 : Bus busy Bus busy flag (BB) 0 : Interrupt request issued 1 : No interrupt request issued I2C-BUS interface interrupt request bit (PIN) 0 : Not detected 1 : Detected Arbitration lost detecting flag (AL) (See note) 0 : Address mismatch 1 : Address match Slave address comparison flag (AAS) (See note) 0 : No general call detected 1 : General call detected General call detecting flag (AD0) (See note) 0 : Last bit = “0 ” 1 : Last bit = “1 ” Last receive bit (LRB) (See note) Note : These bits and flags can be read out, but cannnot be written. Indeterminate 0 W R R — R— R— R— RW RW RW (See note) (See note) (See note) (See note) Fig. 8.6.9 Interrupt Request Signal Generation Timing SCL PIN IICIRQ Note: The START condition duplication prevention function disables the START condition generation, bit counter reset, and SCL output, when the follow- ing condition is satisfied: a START condition is set by another master device. |
Similar Part No. - M37151M6 |
|
Similar Description - M37151M6 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
