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M37151M6 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 35 of 136 REJ03B0129-0100Z 8.6.5 I2C Status Register The I2C status register (address 00F816) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “0016” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in either of the following conditions. • The address data immediately after occurrence of a START con- dition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). • A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” in the following condition. • When the address data is compared with the I2C address regis- ter (8 bits consisting of slave address and RBW), the first bytes match. s The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). (4) Bit 3: arbitration lost✽ detecting flag (AL) In the master transmission mode, when a device other than the mi- crocomputer sets the SDA to “L,” arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.9 shows an interrupt request sig- nal generating timing chart. The PIN bit is set to “1” in any one of the following conditions. • Executing a write instruction to the I2C data shift register (address 00F616). • When the ESO bit is “0” • At reset The conditions in which the PIN bit is set to “0” are shown below: • Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be gen- erated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register (address 00F916) is “0” at reset, the BB flag is kept in the “0” state. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is “0” in the slave reception mode, the TRX bit is set to “1” (transmit) if the ___ least significant bit (R/W bit) of the address data transmitted by the ___ master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. • When arbitration lost is detected. • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication prevention function (Note). • When MST = “0” and a START condition is detected. • When MST = “0” and ACK non-return is detected. • At reset |
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