R1LV1616RBA Series

REJ03C0340-0001 Rev.0.01 2007.10.31

page 8 of 14

Write Cycle

customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. AT any given temperature and voltage condition,

form device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#

going low or UB# going low .

A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#

going high or UB# going high.

5.

6.

7.

Parameter

Symbol

Vcc=2.7V to 3.6V

Unit

Notes

Min.

Max.

Write cycle time

55

-

ns

Address valid to end of write

50

-

ns

Chip selection to end of write

55

-

ns

5

Write pulse width

40

-

ns

4

LB#,UB# valid to end of write

50

-

ns

Address setup time

0

-

ns

6

Write recovery time

0

-

ns

7

Data to write time overlap

25

-

ns

Data hold from write time

0

-

ns

Output active from end of write

5

-

ns

2

Output disable to output in high-Z

0

20

ns

1,2

Write to output in high-Z

0

20

ns

1,2