HN58X2532IAG/HN58X2564IAG

Read from Memory Array (READ):

As shown in the following figure, to send this instruction to the device, chip select (

S) is first driven low. The bits of

the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an

internal address register, and the byte of data at that address is shifted out, on serial data output (Q).

If chip select (

S) continues to be driven low, the internal address register is automatically incremented, and the byte of

data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued

indefinitely. The whole memory can, therefore, be read with a single READ instruction.

The Read cycle is terminated by driving chip select (

S) high. The rising edge of the chip select (S) signal can occur at

any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,

and is not executed, if a Write cycle is currently in progress.

Read from Memory Array (READ) Sequence

S

W

C

D

Q

16-Bit Address

Data Out 2

Data Out 1

01

2

3

4

5

6

7

A0

A1

A2

A3

A13

A14

A15

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

High-Z

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

0

1

2

3

4

5

6

77

Instruction

Note:

1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t

care.

Address Range Bits

Device

HN58X2564IAG

HN58X2532IAG

Address bits

A12 to A0

A11 to A0

Notes: 1. b15-b13 are don’t care on the HN58X2564IAG

2. b15-b12 are don’t care on the HN58X2532IAG

Rev.1.00, Nov.16.2006, page 14 of 20