MOTOROLA CMOS LOGIC DATA

323

MC14502B

Figure 3. Power Dissipation Test Circuit and Waveform

DIS

INH

D1

D2

D3

D4

D5

D6

Q1

Q2

Q3

Q4

Q5

Q6

VDD

ID

PULSE

GENERATOR

CL

CL

CL

CL

CL

CL

Vin

20 ns

20 ns

VDD

VSS

90%

50%

10%

50%

DUTY

CYCLE

Figure 4. AC Test Circuit and Waveforms

(tTLH, tTHL, TPLH, and tPHL)

Figure 5. 3–State AC Test Circuit and Waveforms

(tPHZ, tPLZ, tPZH, tPZL)

Switch Positions for 3–State Test

Test

S1

S2

S3

S4

tPHZ

Open

Closed

Closed

Open

tPLZ

Closed

Open

Open

Closed

tPZL

Closed

Open

Open

Closed

tPZH

Open

Closed

Closed

Open

DISABLE

INHIBIT

D1

D2

D3

D4

D5

D6

Q1

Q2

Q3

Q4

Q5

Q6

CL

16

VDD

8

VSS

PULSE

GENERATOR

20 ns

20 ns

VDD

VSS

VOH

VOL

90%

10%

50%

50%

90%

10%

tPLH

tPHL

tTHL

tTLH

OUTPUT

(TESTS 1 AND 2)

For all tTLH, tTHL, tPHL, and tPLH measurements Vin

may be applied to any other Dn input or to inhibit.

16

VDD

PULSE

GENERATOR

VDD

CL

1 k

S1

S2

VDD

S4

S3

8

VSS

DISABLE

INHIBIT

D1

D2

D3

D4

D5

D6

Q1

Q2

Q3

Q4

Q5

Q6

20 ns

20 ns

VDD

VSS

VOH

tPLZ

tPHZ

tPZH

tPZL

50%

90%

10%

10%

90%

10%

90%

≈ 0.5 V @ VDD = 5 V,

10 V, AND 15 V

≈ 2 V @ VDD = 5 V

≈ 6 V @ VDD = 10 V

≈ 10 V @ VDD = 15 V

VOL

INPUT

DISABLE

Q OUTPUTS