The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM),

organized as 256 words by 8 bits. The multiplexed address and data bus interfaces

directly to 8-bit microprocessors/microcontrollers without any timing or level problems,

e.g. the families SAB 8086, SAB 8051.

All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data

retention is ensured up to

V

chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and

the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR.

The power consumption is max. 5.5

µW in standby mode and max. 16.5 mW in

operation. In standby mode, the power consumption will not increase if the control inputs

are on undefined potential.

Type

Ordering Code

Package

SAE 81C52 P

Q67100-H9017

P-DIP-16-1

SAE 81C52 G

Q67100-H9015

P-DSO-20-1 (SMD)

256 x 8-Bit Static CMOS RAM

NMOS-Compatible

Preliminary DataCMOS IC

SAE 81C52

P-DIP-16-1

P-DSO-20-1

PFeatures

q

256 x 8-bit organization

q

Standby mode

q

Compatible with the NMOS and CMOS versions

of the microprocessor/microcontroller families

SAB 8086, SAB 8051

q

Very low power dissipation

q

Data retention up to

V

q

Three different chip select inputs for two chip

select modes

q

No increasing power consumption in standby mode

if the control inputs are on undefined potential

q

Temperature range – 40 to 110

°C

Semiconductor Group

1

09.94