EMP216MEAW Series

2Mx16 Pseudo Static RAM

Preliminary

Rev 0.0

NOTES (WRITE CYCLE)

transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously

asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#.

Address

High-Z

Data Valid

Data Valid

Data Valid

Data Valid

Data Valid

(A20~A4)

Address

(A3~A0)

CS#

LB#,UB#

WE#

Data In

Data Out