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GS9090B Datasheet(PDF) 7 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 7 Page - Gennum Corporation |
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7 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 7 of 71 14 RESET Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to reset the internal operating conditions to default setting or to reset the JTAG test sequence. Host Mode (JTAG/HOST = LOW): When asserted LOW, all functional blocks will be set to default conditions and all output signals become high impedance with the exception of the STAT pins and the DATA_ERROR pin which will maintain the last state they were in for the duration that RESET is asserted. JTAG Test Mode (JTAG/HOST = HIGH): When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. NOTE: See Device Power Up on page 63 for power on reset requirements. 15, 45 CORE_VDD Non Synchronous Input Power Power supply for digital logic blocks. Connect to +1.8V DC. NOTE: For power sequencing requirements please see Device Power Up on page 63. 16 CS_TMS Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Chip Select / Test Mode Select Host Mode (JTAG/HOST = LOW): CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH): CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. 17 SCLK_TCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Clock / Test Clock. All JTAG / Host Interface address and data are shifted into/out of the device synchronously with this clock. Host Mode (JTAG/HOST = LOW): SCLK_TCK operates as the host interface serial data clock, SCLK. JTAG Test Mode (JTAG/HOST = HIGH): SCLK_TCK operates as the JTAG test clock, TCK. 18, 48 CORE_GND Non Synchronous Input Power Ground connection for digital logic blocks. Connect to GND. 19 SDOUT_TDO Synchronous with SCLK_TCK Output CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW): SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH): SDOUT_TDO operates as the JTAG test data output, TDO. Table 1-1: Pin List and Description (Continued) |
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