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GS9090B Datasheet(PDF) 45 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 45 Page - Gennum Corporation |
45 / 71 page GS9090B Data Sheet 40749 - 2 January 2007 45 of 71 Table 3-14: Host Interface Description for Internal Processing Disable Register Register Name Bit Name Description R/W Default IOPROC_DISABLE Address: 00h 15-10 – Not Used – – 9 ANC_PKT_EXT Ancillary Packet Extraction. When the FIFO is configured for Ancillary Data Extraction mode, this bit must be set HIGH to begin extraction. NOTE: Setting ANC_PKT_EXT LOW will not automatically disable ancillary data extraction (see Section 3.10.3.1). R/W 0 8-7 FIFO_MODE[1:0] FIFO Mode: These bits control which mode the internal FIFO is operating in (see Table 3-15) R/W 0 6 H_CONFIG Horizontal sync timing output configuration. Set LOW for active line blanking timing. Set HIGH for H blanking based on the H bit setting of the TRS word. See Figure 3-3 in Section 3.6.4. R/W 0 5-4 Not Used. 3 ILLEGAL_REMAP Illegal Code re-mapping. Correction of illegal code words within the active picture. Set HIGH to disable. The IOPROC_EN pin must be set HIGH. R/W 0 2 EDH_CRC_INS Error Detection & Handling (EDH) Cyclical Redundancy Check (CRC) error correction insertion. Set HIGH to disable. The IOPROC_EN pin must be set HIGH. R/W 0 1 ANC_CSUM_INS Ancillary Data Checksum insertion. Set HIGH to disable. The IOPROC_EN pin must be set HIGH. R/W 0 0 TRS_INS Timing Reference Signal Insertion. The device will correct TRS based errors when set LOW (see Section 3.9.8.4). The IOPROC_EN pin must also be HIGH. Set this bit HIGH to disable. R/W 0 |
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