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GS9090B Datasheet(PDF) 32 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 32 Page - Gennum Corporation |
32 / 71 page ![]() GS9090B Data Sheet 40749 - 2 January 2007 32 of 71 3.9 Additional Processing Features The GS9090B contains additional processing features that are available in SMPTE mode only (see Section 3.6). 3.9.1 FIFO Load Pulse To aid in the implementation of auto-phasing and line synchronization functions, the GS9090B will generate a FIFO load pulse to reset line-based FIFO storage. This FIFO_LD signal is available for output on one of the multi-function output port pins, if so programmed (see Section 3.12). The FIFO_LD pulse is an active LOW signal which will assert LOW for one PCLK period, generating a FIFO write reset signal. This signal is co-timed to the SAV XYZ code word present on the output data bus. This ensures that the next PCLK cycle will correspond with the first active sample of the video line. NOTE: When the internal FIFO of the GS9090B is set to operate in video mode, the FIFO_LD pulse can be used to drive the RD_RESET input to the device (see Section 3.10.1). Figure 3-6 shows the default timing relationship between the FIFO_LD signal and the output video data. Figure 3-6: FIFO_LD Pulse Timing 3.9.1.1 Programmable FIFO Load Position The position of the FIFO_LD pulse can be moved in PCLK increments from its default position at the SAV XYZ code word to a maximum of one full line from the default position. The offset number of PCLK's must be programmed in the FIFO_LD_POSITION[12:0] internal register (address 28h), via the host interface. The FIFO_LD_POSITION[12:0] register is designed to accommodate the longest SD line length. If a value greater than the maximum line length at the operating SD standard is programmed in this register, the FIFO_LD pulse will not be generated. After a device reset, the FIFO_LD_POSITION[12:0] register is set to zero and the FIFO_LD pulse will assume the default timing. 000 3FF 000 XYZ Y'CbCr DATA PCLK FIFO_LD |
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