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GS9090B Datasheet(PDF) 29 Page - Gennum Corporation

Part # GS9090B
Description  GenLINX짰 III 270Mb/s Deserializer for SDI
Download  71 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9090B Datasheet(HTML) 29 Page - Gennum Corporation

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GS9090B Data Sheet
40749 - 2
January 2007
29 of 71
3.6.4 HVF Timing Signal Generation
The GS9090B extracts timing parameters, and outputs them to the F, V and H pins,
from either the received TRS signals (FW_EN = LOW) or from the internal
flywheel-timing generator (FW_EN = HIGH).
Horizontal blanking period (H), vertical blanking period (V), and field odd / even
timing (F) are extracted and are available for output on any of the multi-function
output port pins, if so programmed (see Section 3.12).
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line-based blanking, or TRS-based
blanking (see Table 3-14 in Section 3.9.8).
Active line-based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H output is HIGH for the entire horizontal blanking period, including the
EAV and SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
output will be HIGH for the entire horizontal blanking period as indicated by the H
bit in the received TRS ID words.
The timing of these signals is shown in Figure 3-3.
NOTE 1: When the internal FIFO is configured for video mode, the H, V, and F
signals will be timed to the data output from the FIFO (see Section 3.10.1).
NOTE 2: When the GS9090B is configured for Low-latency mode, the H, V, and F
output timing will be TRS-based as shown in Section 3.13. Active line-based timing
is not available in this mode, and the setting of the H_CONFIG host interface bit
will be ignored.
Figure 3-3: H,V,F Timing
Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ
(eav)
000
000
3FF
XYZ
(sav)
000
000
3FF
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH


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