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GS9090B Datasheet(PDF) 25 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 25 Page - Gennum Corporation |
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25 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 25 of 71 Figure 3-2: Lock Detection Process The lock detection algorithm (Figure 3-2) first determines if the input is a 270Mb/s serial digital data stream. When the serial data input signal is considered invalid, the LOCKED pin will be set LOW, and all device outputs will be forced LOW, except PCLK. If a valid serial digital input signal has been detected, and the device is in Auto mode, the lock algorithm will attempt to detect the presence of either SMPTE TRS words or DVB-ASI sync words*. Assuming that a valid 270Mb/s SMPTE or DVB-ASI signal has been applied to the device, the LOCKED pin will be set HIGH. The PCLK output frequency will be 27MHz +/- 7.5% when the device is not locked, as well as during the lock detection process. * DVB-ASI sync words must be immediately followed by an MPEG packet header for word alignment to correctly function. For serial inputs that do not conform to SMPTE or DVB-ASI formats, the device can only achieve the locked state in manual mode. In Auto mode, the LOCKED signal will be asserted LOW, the parallel outputs will be latched to logic LOW, and the SMPTE_BYPASS and DVB_ASI output signals will also be set LOW. Power Up or RESET NO YES (Device in Manual Mode) Valid Serial Digital Input? Internal reclocker locked? Device in Auto Mode? (Section 3.6.2) SMPTE TRS or DVB-ASI sync words detected? SMPTE_BYPASS and DVB_ASI pins must be set to support different functionalities (Section 3.6.3). sets SMPTE_BYPASS and DVB_ASI pins LOW Device Device sets LOCKED pin LOW Device sets LOCKED pin HIGH Device sets SMPTE_BYPASS and DVB_ASI status pins (Section 3.6.2) Device outputs accurate 27MHz clock on PCLK pin Device outputs 27MHz +/- 7% clock on PCLK pin Device sets all other output pins LOW (Input data invalid) YES NO NO NO YES YES |
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Similar Description - GS9090B |
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