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GS9090B Datasheet(PDF) 63 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 63 Page - Gennum Corporation |
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63 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 63 of 71 can be accomplished with tri-state buffers used in conjunction with the JTAG/HOST input signal. This is shown in Figure 3-21. Alternatively, if the test capabilities are to be used in the system, the host may still control the JTAG/HOST input signal, but some means for tri-stating the host must exist in order to use the interface at ATE. This is represented in Figure 3-22. Figure 3-21: In-Circuit JTAG Figure 3-22: System JTAG 3.16 Device Power Up The GS9090B has a recommended power supply sequence. To ensure correct power up, power the CORE_VDD pins before the IO_VDD pins. In order to initialize all internal operating conditions to their default state the RESET pin must be held LOW for a minimum of treset = 1ms. (See Figure 3-23) Device pins can be driven prior to power up without causing damage. Application HOST GS9090B CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG_EN In-circuit ATE probe Application HOST GS9090B CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO JTAG_EN In-circuit ATE probe Tri-State |
Similar Part No. - GS9090B |
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Similar Description - GS9090B |
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