 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GS9090B Datasheet(PDF) 60 Page - Gennum Corporation |
|
||||||||||||||||||||||||||||||
GS9090B Datasheet(HTML) 60 Page - Gennum Corporation |
|
|
60 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 60 of 71 All read or write access to the GS9090B is initiated and terminated by the host processor. Each access always begins with a 16-bit command word on SDIN indicating the address of the register of interest. This is followed by a 16-bit data word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode. 3.14.1 Command Word Description The command word consists of a 16-bit word transmitted MSB first and contains a read/write bit, an Auto-Increment bit and a 12-bit address. Figure 3-17 shows the command word format and bit configurations. Command words are clocked into the GS9090B on the rising edge of the serial clock SCLK, which operates in a burst fashion. When the Auto-Increment bit is set LOW, each command word must be followed by only one data word to ensure proper operation. If the Auto-Increment bit is set HIGH, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses from the previous data word. This facilitates multiple address writes without sending a command word for each data word. Auto-Increment may be used for both read and write access. 3.14.2 Data Read and Write Timing Read and write mode timing for the GSPI interface is shown in Figure 3-19 and Figure 3-20 respectively. The timing parameters are defined in Table 3-21. When several devices are connected to the GSPI chain, only one CS must be asserted during a read sequence. During the write sequence, all command and following data words input at the SDIN pin are output at the SDOUT pin as is. Where several devices are connected to the GSPI chain, data can be written simultaneously to all the devices that have CS set LOW. Table 3-21: GSPI Timing Parameters Parameter Definition Specification t0 The minimum duration of time chip select, CS, must be LOW before the first SCLK rising edge. 1.5 ns t1 The minimum SCLK period. 12.5 ns t2 Duty cycle tolerated by SCLK. 40% to 60% t3 Minimum input setup time. 1.5 ns t4 Write Cycle: the minimum duration of time between the last SCLK command (or data word if the Auto-Increment bit is HIGH) and the first SCLK of the data word. 37.1 ns t5 Read Cycle: the minimum duration of time between the last SCLK command (or data word if the Auto-Increment bit is HIGH) and the first SCLK of the data word. 148.4 ns |
Similar Part No. - GS9090B |
|
Similar Description - GS9090B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
