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GS9090B Datasheet(PDF) 6 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 6 Page - Gennum Corporation |
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6 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 6 of 71 Table 1-1: Pin List and Description Pin Number Name Timing Type Description 1 LF- Analog Input Loop filter component connection. Connect to pin 56 (LF+) as shown in Typical Application Circuit (Part B) on page 67. 2 PLL_GND Analog Input Power Ground connection for phase-locked loop. Connect to GND. 3 PLL_VDD Analog Input Power Power supply connection for phase-locked loop. Connect to +1.8V DC. 4 BUFF_VDD Analog Input Power Power supply connection for digital input buffers. When DDI/DDI are AC coupled, this pin should be left unconnected. When DDI/DDI are DC coupled, this pin should be connected to +3.3V as shown in Typical Application Circuit (Part B) on page 67. See Serial Digital Input on page 22 for more details. 5, 6 DDI, DDI Analog Input Serial digital differential input pair. 7 BUFF_GND Analog Input Power Ground connection for serial digital input buffer. Connect to GND. 8 TERM Analog Input Termination for serial digital input. AC couple to BUFF_GND 9, 11 NC – – No connect. 10 VBG Analog Input Bandgap filter capacitor. Connect to GND as shown in Typical Application Circuit (Part B) on page 67. 12 IOPROC_EN Non Synchronous Input CONTROL SIGNAL INPUT Signal Levels are LVCMOS / LVTTL compatible. Used to enable or disable the I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • Illegal Code Remapping • EDH CRC Error Correction • Ancillary Data Checksum Error Correction • TRS Error Correction • EDH Flag Detection To enable a subset of these features, keep the IOPROC_EN pin HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the device will enter low-latency mode. NOTE: When the internal FIFO is configured for Video mode or Ancillary Data Extraction mode, the IOPROC_EN pin must be set HIGH (see Internal FIFO Operation on page 47). 13 JTAG/HOST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are configured as GSPI pins for normal host interface operation. |
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