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GS9090B Datasheet(PDF) 58 Page - Gennum Corporation

Part # GS9090B
Description  GenLINX짰 III 270Mb/s Deserializer for SDI
Download  71 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9090B Datasheet(HTML) 58 Page - Gennum Corporation

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GS9090B Data Sheet
40749 - 2
January 2007
58 of 71
3.13 GS9090B Low-latency Mode
When the IOPROC_EN pin is set LOW, the GS9090B will be set into low-latency
mode. The parallel data will be output with the minimum PCLK latency possible.
The FIFO and all processing blocks except the descrambling and word alignment
blocks will be bypassed when SMPTE_BYPASS is HIGH.
Low-latency mode will also be selected when SMPTE_BYPASS is set LOW,
regardless of the setting of the IOPROC_EN signal (see Table 3-20).
In DVB-ASI mode, the device latency is less than in SMPTE mode.
Data-Through
SMPTE_BYPASS = LOW
DVB_ASI = LOW
STAT0_CONFIG
Output
High Z
000b
STAT1_CONFIG
Output
High Z
000b
STAT2_CONFIG
Output
High Z
000b
STAT3_CONFIG
Output
High Z
000b
Table 3-19: IO_CONFIG Default Configuration
Device Configuration
IO_CONFIG
Register
I/O
Function
Default IO_CONFIG
Setting
Table 3-20: Pin Settings in Low-latency Mode
IOPROC_EN Setting
SMPTE_BYPASS
Setting
Latency (PCLK Cycles)
LOW
LOW
9
HIGH
LOW
10
LOW
HIGH
10
HIGH
HIGH
25
NOTE: Latency applies to parallel processing core only.


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