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GS9090B Datasheet(PDF) 55 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 55 Page - Gennum Corporation |
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55 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 55 of 71 3.10.4 Bypass Mode The internal FIFO is in bypass mode when the FIFO_EN or IOPROC_EN pin is set LOW, or the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 11b. By default, the FIFO_MODE[1:0] bits are set to 11b by the device whenever both the SMPTE_BYPASS and DVB_ASI pins are LOW; however, the FIFO_MODE[1:0] bits may be programed as required. In bypass mode, the FIFO is not inserted into the video path and data is presented to the output of the device synchronously with the PCLK output. The FIFO will be disabled and placed in static mode to save power. 3.11 Parallel Data Outputs The parallel data outputs are clocked out of the device on the rising edge of PCLK as shown in Figure 3-14. Figure 3-14: PCLK to Data & Control Signal Output Timing The output data format is defined by the settings of the external SMPTE_BYPASS and DVB_ASI pins (see Table 3-16). In Manual mode, these pins are set as inputs to the device. In Auto mode, the GS9090B sets these pins as output status signals. 50% tOH tOD VOH VOL VOH VOL VOH VOL VOH VOL CONTROL SIGNAL OUTPUT DOUT[9:0] PCLK Table 3-16: Parallel Data Output Format Pin Settings Output Data Format DOUT[9:0] SMPTE_BYPASS DVB_ASI 10-bit Data DATA LOW LOW 10-bit Multiplexed SD Luma / Chroma HIGH LOW 10-bit DVB-ASI DVB-ASI data LOW HIGH |
Similar Part No. - GS9090B |
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Similar Description - GS9090B |
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