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GS9090B Datasheet(PDF) 53 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 53 Page - Gennum Corporation |
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53 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 53 of 71 The ANC output flag available on the I/O output pin (see Section 3.12) can be used to determine the length of the ancillary data extracted and when to begin reading the extracted data from memory. Recall that ANC is HIGH whenever ancillary data has been detected. In addition, the data count (DC) word, which is located three words after the ancillary data flag (ADF) in the memory, can be read to determine how many valid user data words (UDW) are present in the extracted packet (see SMPTE 291M for more details). The DC value can then be used to preset how many address reads must be performed to obtain only the user data words. Ancillary data will be written into the first half of the FIFO until it is full or until the ANC_DATA_SWITCH bit is toggled (i.e. a HIGH-to-LOW or LOW-to-HIGH transition). If the ANC_DATA_SWITCH bit is not toggled, extracted data will not be written into memory after the first half of the FIFO is full (see block A in Figure 3-13). When the ANC_DATA_SWITCH bit is toggled, new extracted data will be written to the second half starting at address zero (see block B in Figure 3-13). The data in the first half of the FIFO may still be read. Once the data in the first half of the FIFO has been read, the ANC_DATA_SWITCH may be toggled again to enable the second half of the FIFO to be read. The first half of the FIFO will be cleared, and the device will continue to write ancillary data to the second half of the FIFO (see block C in Figure 3-13). If the ANC_DATA_SWITCH bit is toggled again, new extracted data will be written to the first half starting at address zero (see block D in Figure 3-13). The data in the second half of the FIFO may still be read. Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and restore the read and write pointers to the situation shown in block A. The switching process (shown in blocks A to D in Figure 3-13) will continue with each toggle of the ANC_DATA_SWITCH bit. NOTE: At least 1100 PCLK cycles (41us) must pass between toggles of the ANC_DATA_SWITCH bit. Also, the ANC_DATA_SWITCH bit must be toggled at a point in the video where no extraction is occurring (i.e. the ANC signal is LOW). By default, the ancillary data is not removed from the video stream. If desired, the ancillary data may be deleted from the video stream after extraction by setting the ANC_DATA_DELETE bit of the host interface HIGH. In this case, all existing ancillary data will be removed and replaced with blanking values. If any of the ANC_TYPE registers are programmed with a DID and/or a DID and SDID, only the ancillary data packets with the matching ID's will be deleted from the video stream. NOTE: After the ancillary data determined by the ANC_TYPE registers has been deleted, other existing ancillary data may not be contiguous. The device will not concatenate the remaining ancillary data. |
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