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GS9090B Datasheet(PDF) 49 Page - Gennum Corporation

Part # GS9090B
Description  GenLINX짰 III 270Mb/s Deserializer for SDI
Download  71 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9090B Datasheet(HTML) 49 Page - Gennum Corporation

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GS9090B Data Sheet
40749 - 2
January 2007
49 of 71
DVB_ASI pin is set HIGH (i.e. the device is in DVB-ASI mode); however, the
FIFO_MODE[1:0] bits may be programed as required.
Figure 3-10 shows the input and output signals of the FIFO when it is configured
for DVB-ASI Mode.
Figure 3-10: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9090B's FIFO can be used for clock rate
interchange operation. The extracted 8-bit MPEG packets will be written into the
FIFO at 27MHz based on the SYNCOUT signal from the internal DVB-ASI decoder
block. The SYNCOUT and WORDERR bits are also stored in the FIFO (see
Section 3.7.2).
When SYNCOUT goes HIGH, K28.5 stuffing characters have been detected and
no data will be written into the FIFO.
Data is read out of the FIFO using the RD_CLK pin. In DVB-ASI mode, the
RD_RESET pin is not used.
NOTE: With the internal FIFO enabled in DVB-ASI mode, SYNCOUT will always
be LOW since the K28.5 sync characters are not stored in the FIFO.
3.10.2.1 Reading From the FIFO
The FIFO contains internal read and write pointers used to designate which spot in
the FIFO the MPEG packet will be read from or written to. These internal pointers
control the status flags FIFO_EMPTY and FIFO_FULL, which are available for
output on the multi-function output port pins, if so programmed (see Section 3.12).
In the case where the write pointer is originally ahead of the read pointer, the
FIFO_EMPTY flag will be set HIGH when both pointers arrive at the same address
(see block A in Figure 3-12). This flag can be used to determine when to stop
reading from the device.
A write and read pointer offset may be programmed in the
FIFO_EMPTY_OFFSET[9:0] register of the host interface. If an offset value is
programmed in this register, the FIFO_EMPTY flag will be set HIGH when the read
and write pointers of the FIFO are at the same address, and will remain HIGH until
WR_CLK
(PCLK gated with SYNCOUT)
SYNCOUT
WORDERR
FIFO
(DVB-ASI Mode)
RD_CLK
8-bit MPEG Data
8-bit MPEG Data
WORDERR
SYNCOUT
FIFO_FULL
FIFO_EMPTY
Internal
Application Interface


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