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GS9090B Datasheet(PDF) 47 Page - Gennum Corporation |
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GS9090B Datasheet(HTML) 47 Page - Gennum Corporation |
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47 / 71 page  GS9090B Data Sheet 40749 - 2 January 2007 47 of 71 3.10 Internal FIFO Operation The GS9090B contains an internal video line-based FIFO, which can be programmed to work in any of the following modes: 1. Video Mode, 2. DVB-ASI Mode, 3. Ancillary Data Extraction Mode, or 4. Bypass Mode The FIFO can be configured to one of the four modes by using the host interface to set the FIFO_MODE[1:0] bits of the IOPROC_DISABLE register (see Table 3-14 in Section 3.9.8). The setting of these bits is shown in Table 3-15. To enable the FIFO, the FIFO_EN pin must be set HIGH. Additionally, if the FIFO is configured for video mode or ancillary data extraction mode, the IOPROC_EN pin must be set HIGH. The FIFO is fully asynchronous, allowing simultaneous read and write access. It has a depth of 2048 words, which will accommodate 1 full line of SD video for both 525 and 625 standards. The FIFO is 15 bits wide: 10 bits for video data and 5 bits for other signals, such as H, V, F, EDH_DETECT, and ANC. 3.10.1 Video Mode The internal FIFO is in video mode when the FIFO_EN and IOPROC_EN pins are set HIGH, and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 00b. By default, the FIFO_MODE[1:0] bits are set to 00b by the device whenever the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW (i.e. the device is in SMPTE mode); however, the FIFO_MODE[1:0] bits may be programed as required. Figure 3-8 shows the input and output signals of the FIFO when it is configured for video mode. Table 3-15: FIFO Configuration Bit Settings FIFO Mode FIFO_MODE[1:0] Register Setting FIFO_EN Pin Setting IOPROC_EN Pin Setting Video Mode 00b HIGH HIGH DVB-ASI Mode 01b HIGH X Ancillary Data Extraction Mode 10b HIGH HIGH Bypass Mode 11b X X NOTE: ‘X’ signifies ‘don’t care’. The pin is ignored and may be set HIGH or LOW. |
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