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EDS1216AGTA Datasheet(PDF) 17 Page - Elpida Memory

Part # EDS1216AGTA
Description  128M bits SDRAM (8M words 횞 16 bits)
PDF  49 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1216AGTA Datasheet(HTML) 17 Page - Elpida Memory

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EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
17
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
4
L
L
H
H
BA, RA
ACT
Bank and row active*
9
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh*
9
L
L
L
L
MODE
MRS
Mode register set*
8
Remark: H: VIH. L: VIL.
×: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.


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