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MC13110A Datasheet(PDF) 9 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 9 Page - Motorola, Inc |
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9 / 68 page  MC13110A/B MC13111A/B 9 MOTOROLA ANALOG IC DEVICE DATA ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified; Test Circuit Figure 1.) Characteristic Unit Max Typ Min Symbol Measure Pin Input Pin Figure LOW BATTERY DETECT Output Low Voltage (Vin = 1.0 V) 1 Ref1 Ref2 BD1 Out BD2 Out VOL – 0.2 0.4 V BATTERY DETECT INTERNAL THRESHOLD After Electronic Adjustment of VB Voltage 1, 128 VCC Audio BD2 Out V BD Select = (111) CC IBS7 3.381 3.455 3.529 BD Select = (110) IBS6 3.298 3.370 3.442 BD Select = (101) IBS5 3.217 3.287 3.357 BD Select = (100) IBS4 3.134 3.202 3.270 BD Select = (011) IBS3 2.970 3.034 3.098 BD Select = (010) IBS2 2.886 2.948 3.010 BD Select = (001) IBS1 2.802 2.862 2.922 PLL PHASE DETECTOR Output Source Current (VPD = Gnd + 0.5 V to PLL Vref – 0.5 V) – – Rx PD Tx PD IOH – 1.0 – mA Output Sink Current (VPD = Gnd + 0.5 V to PLL Vref – 0.5 V) – – Rx PD Tx PD IOL – 1.0 – mA PLL LOOP CHARACTERISTICS Maximum 2nd LO Frequency (No Crystal) – LO2 In – f2ext – 12 – MHz Maximum 2nd LO Frequency (With Crystal) – – LO2 In LO2 Out f2ext – 12 – MHz Maximum Tx VCO (Input Frequency), Vin = 200 mVpp – – Tx VCO ftxmax – 80 – MHz PLL VOLTAGE REGULATOR Regulated Output Level (IL = 0 mA, after Vref Adjustment) 1 – PLL Vref VO 2.4 2.5 2.6 V Line Regulation (IL = 0 mA, VCC = 3.0 to 5.5 V) 1 VCC Audio PLL Vref VRegLine – 11.8 40 mV Load Regulation (IL = 1.0 mA) 1 VCC Audio PLL Vref VReg Load –20 –1.4 – mV MICROPROCESSOR SERIAL INTERFACE Input Current Low (Vin = 0.3 V, Standby Mode) 1 – Data, Clk, EN IIL –5.0 0.4 – µA Input Current High (Vin = 3.3 V, Standby Mode) 1 – Data, Clk, EN IIH – 1.6 5.0 µA Hysteresis Voltage – – Data, Clk, EN Vhys – 1.0 – V Maximum Clock Frequency – Data, EN, Clk – – – 2.0 – MHz Input Capacitance – Data, Clk, EN – Cin – 8.0 – pF EN to Clk Setup Time 106 – EN, Clk tsuEC – 200 – ns Data to Clk Setup Time 105 – Data, Clk tsuDC – 100 – ns Hold Time 105 – Data, Clk th – 90 – ns Recovery Time 106 – EN, Clk trec – 90 – ns Input Pulse Width – – EN, Clk tw – 100 – ns MPU Interface Power–Up Delay (90% of PLL Vref to Data,Clk, EN) 108 – – tpuMPU – 100 – µs |
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Similar Description - MC13110A |
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