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MC13110A Datasheet(PDF) 57 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 57 Page - Motorola, Inc |
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57 / 68 page  MC13110A/B MC13111A/B 57 MOTOROLA ANALOG IC DEVICE DATA Figure 134. Corner Frequency Programming for 11.15 MHz 2nd LO MC13110A/B MC13111A/B SCF Clock Divider Total Divide Value SCF Clock Freq. (kHz) Rx Upper Corner Frequency (kHz) Tx Upper Corner Frequency (kHz) Scrambler Modulation Frequency (Clk/40) (kHz) Scrambler Lower Corner Frequency (Hz) Scrambler Upper Corner Frequency (kHz) 32 64 174.22 4.092 3.903 4.355 263.7 3.850 32 33 64 66 174.22 168.94 4.092 3.968 3.903 3.785 4.355 4.223 263.7 255.7 3.850 3.733 34 35 68 70 163.97 159 29 3.851 3 741 3.673 3 568 4.099 3 982 248.2 241 1 3.624 3 520 35 70 159.29 3.741 3.568 3.982 241.1 3.520 NOTES: 20. All filter corner frequencies have a tolerance of ±3%. 21. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass Figure 135. Auxiliary Register Latch Bits 4–b 1st LO Capacitor Selection 3–b Test Mode MSB LSB MSB LSB 0 0 0 0 0 0 0 0 0 Figure 136. Digital Test Mode Description TM # TM 2 TM 1 TM 0 Counter Under Test or Test Mode Option “Tx VCO” Input Signal “Clk Out” Output Expected 0 0 0 0 Normal Operation >200 mVpp – 1 0 0 1 Rx Counter 0 to 2.5 V Input Frequency/Rx Counter Value 2 0 1 0 Tx Counter 0 to 2.5 V Input Frequency/Tx Counter Value 3 0 1 1 Reference Counter + Divide by 4/25 0 to 2.5 V Input Frequency/Reference Counter Value * 100 4 1 0 0 SC Counter 0 to 2.5 V Input Frequency/SC Counter Value * 2 5 1 0 1 ALC Gain = 10 Option N/A N/A 6 1 1 0 ALC Gain = 25 Option N/A N/A Auxiliary Register The auxiliary register contains a 4–bit First LO Capacitor Selection latch and a 3–bit Test Mode latch. Operation of these latch bits are explained in Figures 135, 136 and 137. Test Modes Test modes are be selected through the 3–bit Test Mode Register. In test mode, the “Tx VCO” input pin is multiplexed to the input of the counter under test. The output of the counter under test is multiplexed to the “Clk Out” output pin so that each counter can be individually tested. Make sure test mode bits are set to “0’s” for normal operation. Test mode operation is described in Figure 136. During normal operation, the “Tx VCO” input can be a minimum of 200 mVpp at 80 MHz and should be AC coupled. Input signals should be standard logic levels of 0 to 2.5 V and a maximum frequency of 16 MHz. First Local Oscillator Programmable Capacitor Selection There is a very large frequency difference between the minimum and maximum channel frequencies in the 25 Channel U.S. standard. The internal varactor adjustment range is not large enough to accommodate this large frequency span. An internal capacitor with 15 programmable capacitor values can be used to cover the 25 channel frequency span without the need to add external capacitors and switches. The programmable internal capacitor can also be used to eliminate the need to use an external variable capacitor to adjust the 1st LO center frequency during telephone assembly. Figure 32 shows the schematic of the 1st LO tank circuit. Figure 137 shows the register control bit values. The internal programmable capacitor is composed of a matrix bank of capacitors that are switched in as desired. Programmable capacitor values between about 0 and 16 pF can be selected in steps of approximately 1.1 pF. The internal parallel resistance values in the table can be used to calculate the quality factor (Q) of the oscillator if the Q of the external inductor is known. The temperature coefficient of the varactor is 0.08%/ °C. The temperature coefficient of the internal programmable capacitor is negligible. Tolerance on the varactor and programmable capacitor values is ±15%. |
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