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MC13110A Datasheet(PDF) 56 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 56 Page - Motorola, Inc |
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56 / 68 page  MC13110A/B MC13111A/B 56 MOTOROLA ANALOG IC DEVICE DATA Voltage Reference Adjustment An internal 1.5 V bandgap voltage reference provides the voltage reference for the “BD1 Out” and “BD2 Out” low battery detect circuits, the “PLL Vref” voltage regulator, the “VB” reference, and all internal analog ground references. The initial tolerance of the bandgap voltage reference is ±6%. The tolerance of the internal reference voltage can be improved to ±1.5% through MPU serial interface programming. During final test of the telephone, the battery detect threshold is measured. Then, the internal reference voltage value is adjusted electronically through the MPU serial interface to achieve the desired accuracy level. The voltage reference register value should be stored in ROM during final test so that it can be reloaded each time the MC13110A/B or MC13111A/B is powered up (see Figure 131). Figure 131. Bandgap Voltage Reference Adjustment VrefAdj. Bit #3 VrefAdj. Bit #2 VrefAdj. Bit #1 VrefAdj. Bit #0 VrefAdj. # Vref Adj. Amount 0 0 0 0 0 –9.0% 0 0 0 1 1 –7.8% 0 0 1 0 2 –6.6% 0 0 1 1 3 –5.4% 0 1 0 0 4 –4.2% 0 1 0 1 5 –3.0% 0 1 1 0 6 –1.8% 0 1 1 1 7 –0.6% 1 0 0 0 8 +0.6 % 1 0 0 1 9 +1.8 % 1 0 1 0 10 +3.0 % 1 0 1 1 11 +4.2 % 1 1 0 0 12 +5.4 % 1 1 0 1 13 +6.6 % 1 1 1 0 14 +7.8 % 1 1 1 1 15 +9.0 % Switched Capacitor Filter Clock Programming A block diagram of the switched capacitor filter clock divider is show in Figure 132. There is a fixed divide by 2 after the programmable divider. The switched capacitor filter clock value is given by the following equation; (SCF Clock) = F(2nd LO) / (SCF Divider Value * 2). The scrambler modulation clock frequency (SMCF) is proportional to the SCF clock. The following equation defines its value: SMCF = (SCF Clock)/40 The SCF divider should be set to a value which brings the SCF Clock as close to 165.16 kHz as possible. This is based on the 2nd LO frequency which is chosen in Figure 114. Figure 132. SCF Clock Divider Circuit LO2 Out 6–b Programmable SCF Clock Counter LO2 In 2nd LO Crystal SCF Clock Divide By 2.0 Scrambler Modulation Clock Divide By 40 MC13110A/B only Corner Frequency Programming for MC13110A/B and MC13111A/B Four different corner frequencies may be selected by programming the SCF Clock divider as shown in Figures 133 and 134. It is important to note, that all filter corner frequencies will change proportionately with the SCF Clock Frequency and Scrambler Modulation Frequency. The power–up default SCF Clock divider value is 31. Figure 133. Corner Frequency Programming for 10.240 MHz 2nd LO MC13110A/B MC13111A/B SCF Clock Divider Total Divide Value SCF Clock Freq. (kHz) Rx Upper Corner Frequency (kHz) Tx Upper Corner Frequency (kHz) Scrambler Modulation Frequency (Clk/40) (kHz) Scrambler Lower Corner Frequency (Hz) Scrambler Upper Corner Frequency (kHz) 29 58 176.55 4.147 3.955 4.414 267.2 3.902 29 30 58 60 176.55 170.67 4.147 4.008 3.955 3.823 4.414 4.267 267.2 258.3 3.902 3.772 31 32 62 64 165.16 160 00 3.879 3 758 3.700 3 584 4.129 4 000 250.0 242 2 3.650 3 536 32 64 160.00 3.758 3.584 4.000 242.2 3.536 NOTE: 18. All filter corner frequencies have a tolerance of ±3%. 19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass |
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Similar Description - MC13110A |
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