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MC13110A Datasheet(PDF) 51 Page - Motorola, Inc

Part # MC13110A
Description  UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC
Download  68 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC13110A Datasheet(HTML) 51 Page - Motorola, Inc

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MC13110A/B MC13111A/B
51
MOTOROLA ANALOG IC DEVICE DATA
Figure 122. Clock Output Divider
MPU Clk
Bit #2
MPU Clk
Bit #1
MPU Clk
Bit #0
Clk Out
Divider Value
0
0
0
2
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
2.5
1
0
1
20
1
1
0
80
1
1
1
312.5
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 5”. This
provides a MPU clock of about 2.0 MHz after initial
power–up. The reason for choosing a relatively low clock
frequenc y at initial power–up is bec aus e some
microprocessors operate using a 3.0 V power supply and
have a maximum clock frequency of 2.0 MHz. After initial
power–up, the MPU can change the clock divider value and
set the clock to the desired operating frequency. Special care
was taken in the design of the clock divider to insure that the
transition between one clock divider value and another is
“smooth” (i.e. there will be no narrow clock pulses to disturb
the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13110A/B or
MC13111A/B and the microprocessor has the potential to
radiate noise. Problems in the system can occur, especially if
the clock is a square wave digital signal with large high
frequency harmonics. In order to minimize the radiated noise,
a 1000
Ω resistor is included on–chip in series with the “Clk
Out” output driver. A small capacitor or inductor with a
capacitor can be connected to the “Clk Out” line on the PCB
to form a one or two pole low pass filter. This filter should
significantly reduce noise radiated by attenuating the high
frequency harmonics on the signal line. The filter can also be
used to attenuate the signal level so that it is only as large as
required by the MPU clock input. To further reduce radiated
noise, the PCB signal trace length should be kept to a
minimum.
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2 dB gain steps from –14 dB to +16 dB. The
power–up default value for the MC13110A/B and
MC13111A/B is 0 dB. (see Figure 123)
Figure 123. Volume Control
Volume Control
Bit #3
Volume Control
Bit #2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
–14 dB
0
0
0
1
1
–12 dB
0
0
1
0
2
–10 dB
0
0
1
1
3
–8 dB
0
1
0
0
4
–6 dB
0
1
0
1
5
–4 dB
0
1
1
0
6
–2 dB
0
1
1
1
7
0 dB
1
0
0
0
8
2 dB
1
0
0
1
9
4 dB
1
0
1
0
10
6 dB
1
0
1
1
11
8 dB
1
1
0
0
12
10 dB
1
1
0
1
13
12 dB
1
1
1
0
14
14 dB
1
1
1
1
15
16 dB


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