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MC13110A Datasheet(PDF) 45 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 45 Page - Motorola, Inc |
45 / 68 page MC13110A/B MC13111A/B 45 MOTOROLA ANALOG IC DEVICE DATA Data Registers Figure 109 shows the data latch registers and addresses which are used to select each of each registers. Latch bits to the left (MSB) are loaded into the shift register first. The LSB bit must always be the last bit loaded into the shift register. Bits proceeding the register must be “0’s” as shown. Power–Up Defaults for Data Registers When the IC is first powered up, all latch registers are initialized to a defined state. The device is initially placed in the Rx mode with all mutes active. The reference counter is set to generate a 5.0 kHz reference frequency from a 10.24 MHz crystal. The switched capacitor filter clock counter is set properly for operation with a 10.24 MHz crystal. The Tx and Rx counter registers are set for USA handset channel frequency, number 21 (Channel 6 for previous FCC 10 Channel Band). Figure 110 shows the initial power–up states for all latch registers. 6. (00000110) SCF Clock Dividers Latch (MC13111A/B only) 0 6–b Switched Capacitor Filter Clock Counter Latch 4–b Voltage Reference Adjust MSB LSB MSB LSB 3–b Low Battery Detect Threshold Select 00 Figure 109. Microprocessor Interface Data Latch Registers 14–b Tx Counter MSB LSB 1. (00000001) 2. (00000010) 3. (00000011) 4. (00000100) 5. (00000101) 6. (00000110) Latch Address Tx Counter Latch Rx Counter Latch Reference Counter Latch Mode Control Latch Gain Control Latch SCF Clock Dividers Latch (MC13110A/B only) 12–b Reference Counter MSB LSB U.K. BS Select Stdby Mode 4–b Vol Control Rx Mode Tx Mute Rx Mute SP Mute 5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control U.K. HS Select 0 ALC Disable MPU Clk 2 Limiter Disable Clk Disable 0 0 0 0 0 6–b Switched Capacitor Filter Clock Counter Latch 4–b Voltage Reference Adjust MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB 0 MPU Clk 1 MPU Clk 0 3–b Low Battery Detect Threshold Select 14–b Rx Counter MSB LSB 0 IP3 Increase Tx Sbl Bypass 7. (00000111) Auxillary Latch 0 0 0 0 0 0 0 0 0 3–b Test Mode 4–b 1st LO Capacitor Selection Rx Sbl Bypass |
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