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MC13110A Datasheet(PDF) 44 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 44 Page - Motorola, Inc |
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44 / 68 page  MC13110A/B MC13111A/B 44 MOTOROLA ANALOG IC DEVICE DATA SERIAL PROGRAMMABLE INTERFACE Microprocessor Serial Interface The Data, Clock, and Enable (“Data”, “Clk”, and “EN” respectively) pins provide a MPU serial interface for programming the reference counters, the transmit and receive channel divide counters, the switched capacitor filter clock counter, and various other control functions. The “Data” and “Clk” pins are used to load data into the MC13111A/B shift register (Figure 109). Figure 105 shows the timing required on the “Data” and “Clk” pins. Data is clocked into the shift register on positive clock transitions. Figure 105. Data and Clock Timing Requirement Data, Clk, EN Data Clk tsuDC tr tf 50% 50% th 10% 90% After data is loaded into the shift register, the data is latched into the appropriate latch register using the “EN” pin. This is done in two steps. First, an 8–bit address is loaded into the shift register and latched into the 8–bit address latch register. Then, up to 16–bits of data is loaded into the shift register and latched into the data latch register. It is specified by the address that was previously loaded. Figure 106 shows the timing required on the EN pin. Latching occurs on the negative EN transition. Figure 106. Enable Timing Requirement Clk EN tsuEC 50% 50% 50% trec Previous Data Latched Last Clock First Clock 50% The state of the “EN” pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Figure 107 shows the address and data programming diagrams. In the data programming mode, there must not be any clock transitions when “EN” is high. The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the “EN” high state. The convention in these figures is that latch bits to the left are loaded into the shift register first. A minimum of four “Clk” rising edge transition must occur before a negative “EN” transition will latch data or an address into a register. Figure 107. Microprocessor Interface Programming Mode Diagrams Data Latch 8–Bit Address EN Data EN Address Register Programming Mode 16–Bit Data Data Register Programming Mode Latch Latch MSB MSB LSB LSB The MPU serial interface is fully operational within 100 µs after the power supply has reached its minimum level during power–up (see Figure 108). The MPU Interface shift registers and data latches are operational in all four power saving modes; Inactive, Standby, Rx, and Active Modes. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. Figure 108. Microprocessor Serial Interface Power–Up Delay VCC tpuMPU 2.7 V Data, Clk, EN |
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