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MC13110A Datasheet(PDF) 41 Page - Motorola, Inc |
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MC13110A Datasheet(HTML) 41 Page - Motorola, Inc |
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41 / 68 page  MC13110A/B MC13111A/B 41 MOTOROLA ANALOG IC DEVICE DATA By substituting into equation (4), solve for T2: T2 + tan Qp 2 ) p 4 wp (8) By choosing a value for wp and Qp, T1 and T2 can be calculated. The choice of Qp determines the stability of the loop. In general, choosing a phase margin of 45 degrees is a good choice to start calculations. Choosing lower phase margins will provide somewhat faster lock–times, but also generate higher overshoots on the control line to the VCO. This will present a less stable system. Larger values of phase margin provide a more stable system, but also increase lock–times. The practical range for phase margin is 30 degrees up to 70 degrees. The selection of wp is strongly related to the desired lock–time. Since it is quite complicated to accurately calculate lock time, a good first order approach is: T_lock [ 3 wp (9) Equation (9) only provides an order of magnitude for lock time. It does not clearly define what the exact frequency difference is from the desired frequency and it does not show the effect of phase margin. It assumes, however, that the phase detector steps up to the desired control voltage without hesitation. In practice, such step response approach is not really valid. The two input frequencies are not locked. Their phase maybe momentarily zero and force the phase detector into a high impedance mode. Hence, the lock times may be found to be somewhat higher. In general, wp should be chosen far below the reference frequency in order for the filter to provide sufficient attenuation at that frequency. In some applications, the reference frequency might represent the spacing between channels. Any feedthrough to the VCO that shows up as a spur might affect adjacent channel rejection. In theory, with the loop in lock, there is no signal coming from the phase detector. But in practice leakage currents will be supplied to both the VCO and the phase detector. The external capacitors may show some leakage, too. Hence, the lower wp, the better the reference frequency is filtered, but the longer it takes for the loop to lock. As shown in Figure 98, the open loop gain at wp is 1 (or 0 dB), and thus the absolute value of the complex open loop gain as shown in equation (3) solves C1: C1 + K pd KoT1 w2KnT2 1 ) wpT2 2 1 ) wpT1 2 (10) With C1 known, and equation (2) solve C2 and R2: C2 + C1 T2 T1 * 1 (11) R2 + T2 C2 (12) The VCO gain is dependent on the selection of the external inductor and the frequency required. The free running frequency of the VCO is determined by: f + 1 2 p LC T (13) In which L represents the external inductor value and CT represents the total capacitance (including internal capacitance) in parallel with the inductor. The VCO gain can be easily calculated via the internal varicap transfer curve shown below. Figure 99. Varicap Capacitance versus Control Voltage 0 15 14 12 13 11 10 9.0 8.0 7.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 As can be derived from Figure 99, the varicap capacitance changes 1.3 pF over the voltage range from 1.0 V to 2.0 V: DCvar + 1.3 pF V (14) Combining (13) with (14) the VCO gain can be determined by: Ko + 1 jw 1 2 p L C T ) DCvar 2 * 1 2 p L C T ) DCvar 2 (15) Although the basic loopfilter previously described provides adequate performance for most applications, an extra pole may be added for additional reference frequency filtering. Given that the channel spacing in a CT–0 telephone set is based on the reference frequency, and any feedthrough to |
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