4

Jan, 2008

Document Control #ML0019 Rev 2.0

STK16C88-3

SRAM READ CYCLES #1 & #2

Note f:

W must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note g:

Note h:

Measured + 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlledf, g

SRAM READ CYCLE #2: E and G Controlledf

NO.

SYMBOLS

PARAMETER

STK16C88-3-35

UNITS

#1, #2

Alt.

MIN

MAX

1

Chip Enable Access Time

35

ns

2

f, t

ELEH

f

Read Cycle Time

35

ns

3

g

Address Access Time

35

ns

4

Output Enable to Data Valid

15

ns

5

g

Output Hold after Address Change

5

ns

6

Chip Enable to Output Active

5

ns

7

h

Address Change or Chip Disable to Output Inactive

13

ns

8

Output Enable to Output Active

0

ns

9

h

Output Disable to Output Inactive

13

ns

10

e

Chip Enable to Power Active

0

ns

11

d, e

Chip Disable to Power Standby

35

ns

DATA VALID

5

3

DQ (DATA OUT)

ADDRESS

2

6

STANDBY

DATA VALID

8

4

DQ (DATA OUT)

E

ADDRESS

2

G

ACTIVE

1

10

11

7

9

3

27