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STK16C88-3 Datasheet(PDF) 8 Page - Simtek Corporation |
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STK16C88-3 Datasheet(HTML) 8 Page - Simtek Corporation |
8 / 13 page ![]() 8 Jan, 2008 Document Control #ML0019 Rev 2.0 STK16C88-3 The AutoStore+ STK16C88-3 is a fast 32K x 8 SRAM that does not lose its data on power-down. The data is preserved in integral Quantum Trap non- volatile storage elements when power is lost. Auto- matic STORE on power-down and automatic RECALL on power-up guarantee data integrity with- out the use of batteries. NOISE CONSIDERATIONS Note that the STK16C88-3 is a high-speed memory and so must have a high-frequency bypass capaci- tor of approximately 0.1 μF connected between V CC and V SS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK16C88-3 performs a READ cycle whenever E and G are low and W is high. The address speci- fied on pins A 0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initi- ated by an address transition, the outputs will be valid after a delay of t AVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at t ELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the t AVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ 0-7 will be writ- ten into the memory if it is valid t DVWH before the end of a W controlled WRITE or t DVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers t WLQZ after W goes low. AutoStore+ OPERATION The STK16C88-3’s automatic STORE on power- down is completely transparent to the system. The STORE initiation takes less than 500ns when power is lost (V CC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. If the power supply drops faster than 20 μs/volt before Vcc reaches Vswitch, then a 1 ohm resistor should be inserted between Vcc and the system supply to avoid a momentary excess of current between Vcc and internal capacitor. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. POWER-UP RECALL During power up, or after any low-power condition (V CC < VRESET), an internal RECALL request will be latched. When V CC once again exceeds the sense voltage of V SWITCH, a RECALL cycle will automatically be initiated and will take t RESTORE to complete. If the STK16C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10k Ω resistor should be connected either between W and system V CC or between E and system V CC. SOFTWARE NONVOLATILE STORE The STK16C88-3 software STORE cycle is initiated by executing sequential READ cycles from six spe- cific address locations. During the STORE cycle, pre- vious nonvolatile data is erased and then the SRAM contents are written to the nonvolatile storage ele- ments. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is impor- tant that no other READ or WRITE accesses inter- vene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: nvSRAM OPERATION |
Similar Part No. - STK16C88-3_08 |
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Similar Description - STK16C88-3_08 |
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