5

STK16C88-3

Jan, 2008

Document Control #ML0019 Rev 2.0

SRAM WRITE CYCLES #1 & #2

Note i:

If W is low when E goes low, the outputs remain in the high-impedance state.

Note j:

E or W must be

≥ V

SRAM WRITE CYCLE #1: W Controlledj

SRAM WRITE CYCLE #2: E Controlledj

NO.

SYMBOLS

PARAMETER

STK16C88-3-35

UNITS

#1

#2

Alt.

MIN

MAX

12

Write Cycle Time

35

ns

13

Write Pulse Width

25

ns

14

Chip Enable to End of Write

25

ns

15

Data Set-up to End of Write

12

ns

16

Data Hold after End of Write

0

ns

17

Address Set-up to End of Write

25

ns

18

Address Set-up to Start of Write

0

ns

19

Address Hold after End of Write

0

ns

20

h, i

Write Enable to Output Disable

13

ns

21

Output Active after End of Write

5

ns

DATA OUT

E

ADDRESS

W

DATA IN

PREVIOUS DATA

12

16

19

13

18

17

DATA VALID

20

15

HIGH IMPEDANCE

21

14

DATA OUT

E

ADDRESS

12

W

DATA IN

13

DATA VALID

HIGH IMPEDANCE

14

18

17

15

19

16