2

Feb, 2008

Document Control #ML0015 Rev 2.0

STK14C88-3

32-Pin SOIC

32-Pin PDIP

VCC

VCAP

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

29

30

31

32

NC

NC

A13

A14

A8

A9

A11

G

HSB

W

A10

E

A12

A7

A6

A5

A4

A3

A2

A1

A0

Portagee

Joe

DQ0

DQ2

DQ1

VSS

DQ7

DQ6

DQ5

DQ4

DQ3

(TOP)

PIN DESCRIPTIONS

Pin Name

I/O

Description

Input

Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM

E

Input

Chip Enable: The active low E input selects the device

W

Input

Write Enable: The active low W enables data on the DQ pins to be written to the address

location latched by the falling edge of E

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

Power Supply

Power: 3.3V, +0.3V

HSB

I/O

Hardware Store Busy: When low this output indicates a Store is in progress. When pulled

low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor

keeps this pin high if not connected. (Connection Optional).

Power Supply

AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from

SRAM to nonvolatile storage elements.

Power Supply

Ground