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STK14C88 Datasheet(PDF) 4 Page - Simtek Corporation |
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STK14C88 Datasheet(HTML) 4 Page - Simtek Corporation |
4 / 19 page ![]() 4 Feb, 2008 Document Control #ML0014 Rev 2.0 STK14C88 SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%) e Note g: W and HSB must be high during SRAM READ cycles. Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected. Note i: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledg, h SRAM READ CYCLE #2: E and G Controlledg NO. SYMBOLS PARAMETER STK14C88-25 STK14C88-35 STK14C88-45 UNITS #1, #2 Alt. MIN MAX MIN MAX MIN MAX 1tELQV tACS Chip Enable Access Time 25 35 45 ns 2tAVAV g , tELEH g tRC Read Cycle Time 25 35 45 ns 3tAVQV h tAA Address Access Time 25 35 45 ns 4tGLQV tOE Output Enable to Data Valid 10 15 20 ns 5tAXQX h tOH Output Hold after Address Change 5 5 5 ns 6tELQX tLZ Address Change or Chip Enable to Output Active 5 5 5 ns 7tEHQZ i tHZ Address Change or Chip Disable to Output Inactive 10 13 15 ns 8tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9tGHQZ i tOHZ Output Disable to Output Inactive 10 13 15 ns 10 tELICCH f tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICCL f tPS Chip Disable to Power Standby 25 35 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQ X ST AND BY DAT A VAL ID 4 tGL QV DQ (D ATA OUT) E ADDR ESS G ICC AC T IVE 10 tELI CC H 11 tEHI CC L 7 tEHQ Z 8 tGL Q X 1 tEL Q V 9 tGH Q Z 2 tELE H 29 tEHAX 3 tAV QV 27 |
Similar Part No. - STK14C88_08 |
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Similar Description - STK14C88_08 |
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