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STK14C88 Datasheet(PDF) 12 Page - Simtek Corporation |
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STK14C88 Datasheet(HTML) 12 Page - Simtek Corporation |
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12 / 19 page  12 Feb, 2008 Document Control #ML0014 Rev 2.0 STK14C88 • Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). •The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Simtek to understand any impact on the Vcap voltage level at the end of a tRECALL period. PREVENTING STORES The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a V OH of at least 2.2V, as it will have to over- power the internal pull-down device that drives HSB low for 20 μs at the onset of a STORE. When the STK14C88 is connected for AutoStore operation (system V CC connected to VCC and a 68μF capacitor on V CAP) and VCC crosses VSWITCH on the way down, the STK14C88 will attempt to pull HSB low; if HSB doesn’t actually get below V IL, the part will stop try- ing to pull HSB low and abort the STORE attempt. HARDWARE PROTECT The STK14C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs dur- ing low-voltage conditions. When V CAP < VSWITCH, all externally initiated STORE operations and SRAM WRITE s will be inhibited. AutoStore can be completely disabled by tying V CC to ground and applying + 5V to V CAP. This is the AutoStore Inhibit mode; in this mode STOREs are only initiated by explicit request using either the software sequence or the HSB pin. LOW AVERAGE ACTIVE POWER The STK14C88 draws significantly less current when it is cycled at times longer than 50ns. Figure 3 shows the relationship between I CC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial tem- perature range, V CC = 5.5V, 100% duty cycle on chip enable). Figure 4 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. Figure 3: Icc (max) Reads Figure 4: Icc (max) Writes 0 20 40 60 80 100 50 100 150 200 Cycle Time (ns) TTL CMOS 0 20 40 60 80 100 50 100 150 200 Cycle Time (ns) TTL CMOS |
Similar Part No. - STK14C88_08 |
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Similar Description - STK14C88_08 |
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