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M9346-BN3T Datasheet(PDF) 25 Page - STMicroelectronics |
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M9346-BN3T Datasheet(HTML) 25 Page - STMicroelectronics |
25 / 34 page 25/34 M93S66, M93S56, M93S46 Table 19. AC Characteristics (M93Sx6-R) Note: 1. tCHCL + tCLCH ≥ 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office. Test conditions specified in Table 9. and Table 7. Symbol Alt. Parameter Min.3 Max.3 Unit fC fSK Clock Frequency D.C. 1 MHz tPRVCH tPRES Protect Enable Valid to Clock High 50 ns tWVCH tPES Write Enable Valid to Clock High 50 ns tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns tSLCH Chip Select Low to Clock High 250 ns tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH 2 tCS Chip Select Low to Chip Select High 250 ns tCHCL 1 tSKH Clock High Time 250 ns tCLCH 1 tSKL Clock Low Time 250 ns tDVCH tDIS Data In Set-up Time 100 ns tCHDX tDIH Data In Hold Time 100 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns tCHQL tPD0 Delay to Output Low 400 ns tCHQV tPD1 Delay to Output Valid 400 ns tW tWP Erase/Write Cycle time 10 ms |
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