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M58CR064C Datasheet(PDF) 23 Page - STMicroelectronics |
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M58CR064C Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 70 page  23/70 M58CR064C, M58CR064D, M58CR064P, M58CR064Q Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read oper- ation as result of a single address latch cycle. They can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR9, CR5 and CR4 are reserved for future use. Table 9. Configuration Register Bit Description Value Description CR15 Read Select 0 Synchronous Read 1 Asynchronous Read (Default at power-on) CR14 Reserved CR13-CR11 X-Latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 Reserved Other configurations reserved CR10 Power-Down 0 Power-Down disabled 1 Power-Down enabled CR9 Reserved CR8 Wait Configuration 0 WAIT is active during wait state 1 WAIT is active one data cycle before wait state (default) CR7 Burst Type 0 Interleaved 1 Sequential (default) CR6 Valid Clock Edge 0 Falling Clock edge 1 Rising Clock edge CR5-CR4 Reserved CR3 Wrap Burst 0 Wrap 1 No Wrap CR2-CR0 Burst Length 001 4 words 010 8 words 111 Continuous (CR7 must be set to ‘1’) |
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