M58CR064C datasheet(20/70 Pages) STMICROELECTRONICS

Part #	M58CR064C

Description	64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

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STATUS REGISTER

The M58CR064 has two Status Registers, one for

each bank. The Status Registers provide informa-

tion on the current or previous Program or Erase

operations executed in each bank. Issue a Read

Status Register command to read the contents of

the Status Register, refer to Read Status Register

Command section for more details. To output the

contents, the Status Register is latched and updat-

ed on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

or Output Enable returns to VIH. The Status Reg-

ister can only be read using single asynchronous

or single synchronous reads. Bus Read opera-

tions from any address within the bank, always

read the Status Register during Program and

Erase operations.

The various bits convey information about the sta-

tus and any errors of the operation. Bits SR7, SR6

and SR2 give information on the status of the bank

and are set and reset by the device. Bits SR5,

SR4, SR3 and SR1 give information on errors,

they are set by the device but must be reset by is-

suing a Clear Status Register command or a hard-

ware reset. If an error bit is set to ‘1’ the Status

Register should be reset before issuing another

command.

The bits in the Status Register are summarized in

Table 8, Status Register Bits. Refer to Table 8 in

conjunction with the following text descriptions.

Program/Erase Controller Status Bit (SR7). The

Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive in the addressed bank. When the Pro-

gram/Erase Controller Status bit is Low (set to ‘0’),

the Program/Erase Controller is active; when the

bit is High (set to ‘1’), the Program/Erase Control-

ler is inactive, and the device is ready to process a

new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, VPP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status Bit (SR6). The

Erase

Suspend Status bit indicates that an Erase opera-

tion has been suspended or is going to be sus-

pended in the addressed block. When the Erase

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

SR7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status Bit (SR5). The Erase Status bit

can be used to identify if the memory has failed to

verify that the block or bank has erased correctly.

When the Erase Status bit is High (set to ‘1’), the

Program/Erase Controller has applied the maxi-

mum number of pulses to the block or bank and

still failed to verify that it has erased correctly. The

Erase Status bit should be read once the Program/

Erase Controller Status bit is High (Program/Erase

Controller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status Bit (SR4). The Program Status

bit is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

VPP Status Bit (SR3). The VPP Status bit can be

used to identify an invalid voltage on the VPP pin

during Program and Erase operations. The VPP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if VPP becomes invalid during an operation.

When the VPP Status bit is Low (set to ‘0’), the volt-

age on the VPP pin was sampled at a valid voltage;

when the VPP Status bit is High (set to ‘1’), the VPP

pin has a voltage that is below the VPP Lockout

Voltage, VPPLK, the memory is protected and Pro-

gram and Erase operations cannot be performed.

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